1. Field of the Invention
The invention relates to a field effect transistor and a method of fabricating the same, and more particularly to a field effect transistor as a highly reliable, high-performance chemical compound electronic device operating in a range of microwaves and millimeter waves, and a method of fabricating the same.
2. Description of the Related Art
In these days, ternary and quaternary mixed crystal semiconductor such as InGaAs and InGaAsP have attracted attention. Among them, InGaAs matching in lattice to an InP substrate is in particular suitable to optical devices and material of which field effect transistors are made. In particular, a field effect transistor employing two-dimensional electron gas at a hetero-interface between InP and InAlAs has been much studied. The reasons why InGaAs is promising as an electron transfer device in comparison with GaAs and so on are as follows:
(a) a peak value at electron drift velocity is greater;
(b) mobility of an electron at a low intensity electric field is greater;
(c) it is easier to form ohmic electrodes with the result of smaller contact resistance;
(d) greater overshoot in an electron speed can be expected;
(e) smaller noise caused by root scattering; and
(f) better characteristics with respect to an interface with insulating materials. In addition, it is one of major reasons to be able to accomplish a two-dimensional electron gas device.
A field effect transistor employing two-dimensional electron gas at an interface between InGaAs and InAlAs is presently considered promising as a high performance microwave milliwave device, and is researched and developed. In particular, the above-mentioned field effect transistor has been confirmed to be effective as a low-noise device in experiments. For instance, as reported by K. H. G. Duh et al. in xe2x80x9cA Super Low-Noise 0.1 xcexcm T-Gate InAlAs-InGaAs-InP HEMTxe2x80x9d, IEEE MICROWAVE AND GUIDED WAVE LETTERS. Vol. 1, No. 5, May 1991, pp. 114-116, noise figure of 1.2 dB and associated gain of 7.2 dB at 94 GHz in room temperature have been confirmed. The device having been reported by Duh was made of material accomplishing lattice match on an InP substrate, that is, In0.53Ga0.47As/In0.52Al0.48As, and material defining In composition. In the device, two-dimensional electron gas is formed in the In0.53Ga0.47As layer.
In order to enhance performance of the device, for instance, an attempt was made by G. I. NG et al. in xe2x80x9cImproved Strained HEMT Characteristics Using Double-Heterojunction In0.65Ga0.35As/Ino0.52Al0.48As Designxe2x80x9d, IEEE ELECTRON DEVICE LETTERS, Vol. 10, No. 3, March 1989, pp. 114-116, where In composition in an InGaAs layer constituting a channel was arranged to have a figure greater than 0.53.
Recently, various high performances of a device have been reported in the field of InAlAs/InGaAs family hetero-junction field effect transistor. On the other hand, thermally unstable factors have been also reported. That is, impurities such as fluorine which is not a constituent of a device enter an epitaxial layer from outside to thereby inactivate donor in an impurity containing InAlAs layer usually used as a donor layer.
For instance, Hayafuji has reported degradation of a device caused by fluorine in xe2x80x9cThermal stability of AlInAs/GaInAs/InP heterostructurexe2x80x9d, Applied Physics Letters, Vol. 66, No. 7, February 1995, pp. 863-865. For another instance, Takahashi has reported degradation of a device caused by oxygen in xe2x80x9cThermal Stability of Al0.48In0.52As/Ga0.47In0.53As/InP Heterostructure and its Improvement by Phosphidizationxe2x80x9d, Proceedings of 7th International Conference of InP and Related Materials, 1995, pp. 597-600.
Fujihara et al. reported in Technical Report of IEICE ED95-105, pp. 13-20 that impurities entering an epitaxial layer are reduced in an amount by decreasing a composition rate of Al in an InAlAs Schottky layer formed on an InAlAs donor layer. That is, when a donor layer is composed of InAlAs, the thermal instability may be eliminated by forming a barrier layer on the donor layer for preventing impurities from entering to the donor layer. Fujihara reported conducting experiment in which there were formed samples of InAlGaAs Schottky layers containing no impurities and having different composition rates between Al and Ga, and the samples stood in heated condition. The result of the experiment was that as a composition rate of Al was decreased, fluorine entering an epitaxial layer was reduced in an amount and further a reduction of a sheet electron density was stopped.
As an example for enhancing reliability of a device in a similar manner, Fujihara et al. suggested a field effect transistor in xe2x80x9cThermally stable InAlAs/InGaAs heterojunction FET with AlAs/InAs superlattice insertion layerxe2x80x9d, ELECTRONICS LETTERS, May 23, 1996, Vol. 32, No. 11, pp. 1039-1041. In the suggested field effect transistor, a superlattice layer composed of AlAs and InAs is inserted between a donor layer and a gate forming layer. It is reported that the field effect transistor can prevent intrusion of fluorine thereinto, and stop thermal degradation.
As an example of an InP layer used as a barrier layer, Enoki et al. has suggested a structure in xe2x80x9c0.1xe2x88x92xcexcm InAlAs/InGaAs HEMTS WITH AN InP-RECESS-ETCH STOPPER GROWN BY MOCVDxe2x80x9d, Proceedings of 7th International Conference of InP and Related Materials, 1995, pp. 81-84. It is reported that an InP layer as a gate contact layer is formed on an InAlAs layer to thereby enhance uniformity of device characteristics in a wafer.
As mentioned above, when a donor layer is composed of InAlAs, inactivation of donor caused by intrusion of impurities thereinto is a major problem significantly reducing reliability of a device. In most of heterojunction field effect transistors to be formed on an InP substrate, a donor source layer is generally composed of an InAlAs layer. To the contrary, a transistor which does not employ InAlAs, but employs InP for a donor layer has been suggested by A. M. Kxc3xcsters et al. in IEEE ELECTRON DEVICE LETTERS, Vol. 16, No. 9, 1995, pp. 396-398. The suggested transistor avoids inactivation of donor caused by intrusion of impurities such as fluorine by not employing InAlAs for a donor source layer, to thereby ensure thermal reliability.
As mentioned earlier, a major problem for reducing reliability in an InALAs/InGaAs heterojunction transistor is that impurities such as fluorine present in an atmosphere or fluorine adhered to a surface of a sample in a process enters an epitaxial layer while a device is held in heated condition, resulting in that donor in an InAlAs layer containing n-type impurities therein is inactivated.
One of objects of the present invention is to solve this problem by providing a highly reliable high performance InAlAs/InGaAs family heterojunction transistor. One of solutions to the problem is to insert a barrier layer between an InAlAs donor layer and a gate electrode for preventing intrusion of impurities into an epitaxial layer. Up to now, it has been found out by experiments that intrusion of impurities into an epitaxial layer can be prevented by employing material other than InAlAs and AlGaAs, as having been reported by Hayafuji, Fujihara and Enoki.
However, the use of a barrier layer is accompanied with other problems. If a barrier layer had positive conduction band discontinuity to material of which a cap layer is composed, since an ohmic electrode is formed on the barrier layer, a source resistance would be increased with the result of deterioration of performance of a device. Since a cap layer is usually composed of InGaAs, the barrier layers employed in the above-mentioned prior art are accompanied with another problem of an increased source resistance.
In addition, since crystal quality of a barrier layer exerts a major influence on crystal quality of a layer to be formed on the barrier layer, it would be absolutely necessary to determine crystal growth conditions each time when a device is fabricated.
Apart from the above-mentioned prior art, various InAlAs/InGaAs family heterojunction transistors have been suggested as follows.
In xe2x80x9cDouble-Heterojunction Lattice-Matched and Pseudomorphic InGaAs HEMT with xcex4-Doped InP Supply Layers and p-InP Barrier Enhancement Layer Grown by LP-MOVPExe2x80x9d, IEEE ELECTRON DEVICE LETTERS, Vol. 14, No. 1, January 1993, A. M. Kxc3xcsters et al. have suggested a LP-MOVPE-grown double-hetrojuction HEMT (DH-MEMT) with InP as carrier-supplying and barrier layers that avoid the kink effect due to Al-containing layers.
Japanese Unexamined Patent Publication No. 4-180240 has suggested a field effect transistor including an InP substrate and an InGaAs layer formed on the InP substrate, wherein the InGaAs layer has an In composition rate greater than 0.53 at which the InGaAs layer is lattice-matched with the InP substrate.
Japanese Unexamined Patent Publication No. 6-232175 has suggested InXAl1xe2x88x92XAs/InYGa1xe2x88x92YAs heterojunction type field effect transistor lattice-matched with an InP substrate, wherein pseudo-morphic undoped AlZGa1xe2x88x92As layer is inserted below a gate electrode, and an n-type GaAs layer is formed on the undoped AlZGa1xe2x88x92ZAs layer in source/drain regions.
Japanese Unexamined Patent Publication No. 6-236898 has suggested a field effect transistor, in which an I-type In0.52Al0.48As buffer layer, an I-type In1xe2x88x92XGaXAsYP1xe2x88x92Y channel layer, an In0.52Al0.48As spacer layer, an n-type In0.52A0.48As electron supply layer, an I-type In0.52Al0.48As Schottky layer, and n-type Ino0.53Ga0.47As cap layer are grown on a semi-insulating InP substrate. A gate electrode is formed on a recess formed in the n-type In0.53Ga0.47As cap layer, and source and drain electrodes are formed at opposite sides of the gate electrode.
Japanese Unexamined Patent Publication No. 6-302625 has suggested a field effect transistor including n-In0.49Ga0.51P etching stopper layer, n-Al XGa 1xe2x80x94XAs layer, and a GaAs cap layer on an operation layer. A gate electrode is formed on the n-In0.49Ga0.51P etching stopper layer.
Japanese Unexamined Patent Publication No. 7-111327 has suggested a heterojunction field effect transistor wherein a non-doped In0.52Al0.48As buffer layer, a non-doped In0.80Ga0.20As channel layer, a non-doped In0.52Al0.48As spacer layer, an n-type In0.52Al0.48As doped layer, a non-doped In0.52Al0.48As gate contact layer, a non-doped In0.80Ga0.20As resistance reducing layer, and an n-type In0.53Ga0.47As cap layer are formed in this order on a semi-insulating InP substrate. The field effect transistor is characterized by the non-doped In0.53 Ga0.20As inserted between the non-doped In0.52Al0.48As gate contact layer and the n-type In0.53Ga0.47As cap layer.
Japanese Unexamined Patent Publication No. 7-312421 has suggested a field effect transistor wherein an InGaAs active layer, an InAlAs layer, a GaAs layer, and an InGaAs cap layer are formed on an InP substrate. A gate electrode is formed on the GaAs layer. A layer made of metal having a melting point at 1600xc2x0 C. or greater is sandwiched between the gate electrode and the GaAs layer. N-type impurities are implanted into a part of the InAlAs layer.
It is an object of the present invention to provide a field effect transistor as a microwave milliwave compound device capable of avoiding thermal instability caused by impurities entering a donor layer to thereby cause donor to be inactivated, and also provide a method of fabricating the same.
In one aspect of the present invention, there is provided a field effect transistor including (a) a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, (b) a gate base layer formed on the recess and composed of one of an InP layer and a plurality of layers including an InP layer, and (c) a gate electrode formed on the gate base layer.
There is further provided a field effect transistor including (a) a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, (b) a gate base layer formed on the recess and composed of one of an InGaP layer and a plurality of layers including an InGaP layer, and (c) a gate electrode formed on the gate base layer.
There is still further provided a field effect transistor including (a) a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, (b) a gate base layer formed on the recess and composed of one of an AlXGa1xe2x88x92XAs (0xe2x89xa6Xxe2x89xa61) layer and a plurality of layers including an AlXGa1xe2x88x92XAs (0xe2x89xa6Xxe2x89xa61) layer, and (c) a gate electrode formed on the gate base layer.
There is yet further provided a field effect transistor including (a) a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, (b) a gate base layer formed on the recess and composed of one of an InXGa1xe2x88x92As (0xe2x89xa6Xxe2x89xa61) layer and a plurality of layers including an InXGa1xe2x88x92X As (0xe2x89xa6Xxe2x89xa61) layer, and (c) a gate electrode formed on the gate base layer.
There is still yet further provided a field effect transistor including (a) a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, (b) a gate base layer formed on the recess and composed of one of an InXAl1xe2x88x92XAs (0xe2x89xa6X less than 0.4 or 0.6 less than Xxe2x89xa61) layer and a plurality of layers including an InXAl1xe2x88x92XAs (0xe2x89xa6X less than 0.4 or 0.6 less than Xxe2x89xa61) layer, and (c) a gate electrode formed on the gate base layer.
The above-mentioned field effect transistor may further include an InAlAs or AlGaAs layer containing no impurities therein, formed between the gate base layer and the gate electrode. For instance, the semi-insulating semiconductor substrate may be composed of GaAs or InP.
In another aspect of the present invention, there is provided a method of fabricating a field effect transistor, including the steps of (a) forming a recess with a semi-insulating semiconductor substrate at a region in which a gate is to be formed, (b) forming a gate base layer on the recess, the gate base layer being composed of one of an InP layer and a plurality of layers including an InP layer, and (c) forming a gate electrode on the gate base layer.
There is further provided a method of fabricating a field effect transistor, including the steps of (a) forming a recess with a semi-insulating semiconductor substrate at a region in which a gate is to be formed, (b) forming a gate base layer on the recess, the gate base layer being composed of one of an InGaP layer and a plurality of layers including an InGaP layer, and (c) forming a gate electrode on the gate base layer.
There is still further provided a method of fabricating a field effect transistor, including the steps of (a) forming a recess with a semi-insulating semiconductor substrate at a region in which a gate is to be formed, (b) forming a gate base layer on the recess, the gate base layer being composed of one of an AlXGa1xe2x88x92XAs (0xe2x89xa6Xxe2x89xa61) layer and a plurality of layers including an AlXGa1xe2x88x92XAs (0xe2x89xa6Xxe2x89xa61) layer, and (c) forming a gate electrode on the gate base layer.
There is yet further provided a method of fabricating a field effect transistor, including the steps of (a) forming a recess with a semi-insulating semiconductor substrate at a region in which a gate is to be formed, (b) forming a gate base layer on the recess, the gate base layer being composed of one of an InXGa1xe2x88x92XAs (0xe2x89xa6Xxe2x89xa61) layer and a plurality of layers including an InXGa1xe2x88x92XAs (0xe2x89xa6Xxe2x89xa61) layer, and (c) forming a gate electrode on the gate base layer.
There is still yet further provided a method of fabricating a field effect transistor, including the steps of (a) forming a recess with a semi-insulating semiconductor substrate at a region in which a gate is to be formed, (b) forming a gate base layer on the recess, the gate base layer being composed of one of an InXAl1xe2x88x92XAs (0xe2x89xa6X less than 0.4 or 0.6 less than Xxe2x89xa61) layer and a plurality of layers including an InXAl1xe2x88x92XAs (0xe2x89xa6X less than 0.4 or 0.6 less than Xxe2x89xa61) layer, and (c) forming a gate electrode on the gate base layer.
The above-mentioned method may further include the step (d) of forming an InAlAs or AlGaAs layer containing no impurities therein, between the gate base layer and the gate electrode, the step (d) being to be carried out between the steps (b) and (c).
One of keys of the present invention is to form a barrier layer below a gate electrode. The barrier layer is composed of material which does not allow impurities to pass therethrough in order to prevent InAlAs and AlGaAs layers, to which n-type impurities are implanted and which are readily contaminated with impurities such as fluorine, from being exposed outside. However, when the InAlAs and AlGaAs layers are crystal-grown in usual planar state, the formation of a barrier layer below a gate electrode may be accompanied with problems such as an increase of a source resistance and gate leakage. In addition, if a barrier layer is formed directly below a gate electrode, crystal growth conditions have to be determined in detail and/or a barrier layer may have a thickness limitation in order to avoid degradation in quality of a cap layer to be formed on a barrier layer. Hence, in accordance with the present invention, a recess is first formed, then a barrier layer and a gate contact layer are selectively grown within the recess, and finally a gate electrode is formed on the barrier layer.
The field effect transistor in accordance with the present invention prevents thermal instability thereof caused by impurities such as fluorine entering a donor layer to thereby inactivate donor. As a result, there is presented a highly reliable compound field effect transistor to be formed on an InP substrate.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.